1. Technical Field
The present invention relates to test circuit design, and more particularly to creating test circuits for high-resolution picosecond imaging circuit analysis.
2. Description of the Related Art
Picosecond imaging circuit analysis (PICA) is a technique used for timing measurement and failure analysis of integrated circuits. PICA exploits a side-effect of field effect transistors (FETs) whereby a FET emits a burst of light when its drain region is at a high voltage and its gate transitions from a low voltage to a high voltage. This allows for optical imaging of the back side of an integrated chip circuit to, e.g., locate failed transistors and perform other measurements.
In PICA systems, higher resolutions are desirable to ensure good imaging that can test the limits of circuit design features. To test the resolution of PICA systems, test circuits are created which are designed to produce optical emissions that are close together. Previous attempts to create such test circuits involved compressing circuit layouts parallel and perpendicular to FET gates. Compression parallel to the transistor gate is limited by either polysilicon gate later end-to-end spacing or n-channel metal-oxide-semiconductor to p-channel metal-oxide-semiconductor spacing. Compression parallel to the transistor gate is limited by gate pitch. Exemplary spacings according to such prior art technologies include 284 nm in the parallel spacing and 220 nm in the perpendicular spacing. As such, previous attempts to create PICA test circuits have been limited in their ability to test PICA resolution.